The present invention relates generally to computer systems, and more particularly to power management in a multi-core processing system.
In computer systems that include multiple processing resources for executing a plurality of tasks, distribution of task execution is important to system performance. In systems having multiple processor cores and multi-threading operation, allocation of tasks or threads among cores can affect power consumption. Power management can impact overall computer system operating costs, processing system responsiveness, and expected operating life of individual components or subsystems.
Some computer systems support dynamic power management by including multiple independent power control actuators. Power control actuators are typically incorporated into independently architected control loops with single actuators, such as a dynamic voltage and frequency scaling (DVFS) actuator, a core folding (CF) actuator, and a per-core power gating (PCPG) actuator. A DVFS actuator can control voltage and frequency of a multi-core processor. A CF actuator can control consolidation or distribution of threads in processor cores. A PCPG actuator can turn power on or off for individual processor cores. When power control actuators are deployed in the same computer system and operate independently at the same time, conflicting scenarios can result in one power control actuator negating the intended effect of another power control actuator. Decoupled power control loops can be simpler to independently test or verify; however, the net effect may not be desirable. For example, a CF controller may decide to unfold (and power on) some processor cores and as a result, the utilization of the turned-on processor cores can drop. A DVFS controller may observe the reduced utilization and lower a processor frequency to keep the processor cores highly utilized. Reducing the processor frequency may hurt performance and negate the effect intended by the CF controller.